Texas Instruments /MSP432P401M /EUSCI_A2 /UCAxCTLW0

Software reset enable

0 (UCSWRST_0): Disabled. eUSCI_A reset released for operation

1 (UCSWRST_1): Enabled. eUSCI_A logic held in reset state

Transmit break

0 (UCTXBRK_0): Next frame transmitted is not a break

1 (UCTXBRK_1): Next frame transmitted is a break or a break/synch

Transmit address

0 (UCTXADDR_0): Next frame transmitted is data

1 (UCTXADDR_1): Next frame transmitted is an address

Dormant

0 (UCDORM_0): Not dormant. All received characters set UCRXIFG.

1 (UCDORM_1): Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG.

Receive break character interrupt enable

0 (UCBRKIE_0): Received break characters do not set UCRXIFG

1 (UCBRKIE_1): Received break characters set UCRXIFG

Receive erroneous-character interrupt enable

0 (UCRXEIE_0): Erroneous characters rejected and UCRXIFG is not set

1 (UCRXEIE_1): Erroneous characters received set UCRXIFG

eUSCI_A clock source select

0 (UCSSEL_0): UCLK

1 (UCSSEL_1): ACLK

2 (UCSSEL_2): SMCLK

Synchronous mode enable

0 (UCSYNC_0): Asynchronous mode

1 (UCSYNC_1): Synchronous mode

eUSCI_A mode

0 (UCMODE_0): UART mode

1 (UCMODE_1): Idle-line multiprocessor mode

2 (UCMODE_2): Address-bit multiprocessor mode

3 (UCMODE_3): UART mode with automatic baud-rate detection

Stop bit select

0 (UCSPB_0): One stop bit

1 (UCSPB_1): Two stop bits

Character length

0 (UC7BIT_0): 8-bit data

1 (UC7BIT_1): 7-bit data

MSB first select

0 (UCMSB_0): LSB first

1 (UCMSB_1): MSB first

Parity select

0 (UCPAR_0): Odd parity

1 (UCPAR_1): Even parity

Parity enable

0 (UCPEN_0): Parity disabled

1 (UCPEN_1): Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation.